Methods of Communicating Data Using Inversion and Related Systems

ABSTRACT

A method may be provided to communicate a plurality of groups of output data bits representing a respective plurality of groups of input data bits over a data bus with each group of output data bits and each group of input data bits have an equal data width. Each of the plurality of groups of input data bits at may be received at a data register. For each group of input data bits received at the data register, if a number of data bits of the group of input data bits having a first logic level is greater than half of the data width, the group of input data bits are inverted, the inverted group of input data bits are transmitted as a respective group of output data bits in parallel over the data bus, and an inversion flag associated with the respective group of output data bits is transmitted. For each group of input data bits received at the data register, if a number of data bits of the group of input data bits having a second logic level different than the first logic level is greater than half of the data width, the group of input data bits is transmitted without inversion as a respective group of output data bits in parallel over the data bus, and a non-inversion flag associated with the respective group of output data bits is transmitted. Related systems are also discussed.

RELATED APPLICATION

This application claims the benefit of priority as a divisional of U.S.application Ser. No. 11/818,165 filed Jun. 13, 2007, which claims thebenefit of Korean Patent Application No. 10-2006-0076726, filed on Aug.14, 2006, in the Korean Intellectual Property Office. The disclosures ofboth of the above referenced applications are hereby incorporated hereinin their entireties by reference.

FIELD OF THE INVENTION

The present invention relates to electronics, and more particularly, tomethods of processing data and related systems.

BACKGROUND

Methods of transmitting data between semiconductor devices through atransmission line include low voltage complimentary metal oxidesemiconductor (LVCMOS) signaling and pseudo open drain (POD) signaling.FIG. 1A illustrates a memory system 10 using LVCMOS signaling. Referringto FIG. 1A, the memory system 10 includes a semiconductor memory device11 such as a dynamic random access memory (DRAM), transmission lines 16corresponding to data buses, and a memory controller 17.

The semiconductor memory device 11 may include a plurality oftransceivers 12 and data input/output pads (or DQ pads) 15. Each of thetransceivers 12 includes an output driver 13 and an input buffer 14. Thememory controller 17 controls a data read operation and a data writeoperation of the semiconductor memory device 11. The memory controller17 includes a plurality of transceivers 18 and DQ pads 21. Each of thetransceivers 18 includes an output driver 19 and an input buffer 20.

The output driver 13 of the semiconductor memory device 11 may be aninverter type of driver including a PMOS transistor and an NMOStransistor or a buffer type of driver. The output driver 13 of thesemiconductor memory device 11 drives the transmission line 16 having acharacteristic impedance of 50 ohms, for example, with a power supplyvoltage VDDQ or a ground voltage VSSQ to transmit data to the inputbuffer 20 of the memory controller 17.

The output driver 19 of the memory controller 17 may be an inverter typeof driver including a PMOS transistor and an NMOS transistor or a buffertype of driver. The output driver 19 of the memory controller 17 drivesthe transmission line 16 with the power supply voltage VDDQ or theground voltage VSSQ to transmit data to the input buffer 14 of thesemiconductor memory device 11.

In LVCMOS signaling, the voltage of the transmission line 16 variesbetween the power supply voltage VDDQ (a high level) and the groundvoltage VSSQ (a low level). Accordingly, a data signal swing range inthe transmission line 16 may be relatively large, and thus LVCMOSsignaling may be used in a relatively low-frequency operation of thememory system 10. The low-frequency of the memory system 10 may be afrequency lower than about 300 MHz. When data is transmitted through thetransmission line 16 according to LVCMOS signaling, there may be nodirect current (DC) power component and only an alternating current (AC)power component may exist. Accordingly, LVCMOS signaling may providerelatively low power consumption.

FIG. 1B illustrates a memory system 20 using POD signaling. Referring toFIG. 1B, the memory system 20 may include a semiconductor memory device21, transmission lines 27 corresponding to data buses, and a memorycontroller 28.

The semiconductor memory device 21 may be a graphic double data ratesynchronous dynamic random access memory (DRAM). The semiconductormemory device 21 may include a plurality of transceivers 22 and DQ pads26. Each of the transceivers 22 may include an output driver 23, atermination resistor RT1, a switch 24 and an input buffer 25. Thetermination resistor RT1 (having a terminal connected to the source of apower supply voltage VDDQ) and the switch 24 may provide an on dietermination (ODT) circuit. The ODT circuit is a termination matchingcircuit that may reduce data distortion due to reflection of datatransmitted through the transmission line 27. The ODT circuit may beactivated when the switch 24 is turned on.

The memory controller 28 may control a data read operation and a datawrite operation of the semiconductor memory device 21. The memorycontroller 28 includes a plurality of transceivers 29 and DQ pads 33.Each of the transceivers 29 may include an output driver 30, atermination resistor RT2, a switch 31 and an input buffer 32. Thetermination resistor RT2 (having a terminal connected to the source of apower supply voltage VDDQ) and the switch 31 may provide an ODT circuitthat is activated when the switch 31 is turned on.

The output driver 23 of the semiconductor memory device 21 may be aninverter type of driver including a PMOS transistor and an NMOStransistor or a buffer type of driver. The output driver 23 of thesemiconductor memory device 21 may drive the transmission line 27 havinga characteristic impedance of 50 ohm, for example, with the power supplyvoltage VDDQ or a ground voltage VSSQ to transmit data to the inputbuffer 32 of the memory controller 28. When data is transmitted to theinput buffer 32 of the memory controller 28, the ODT circuit of thesemiconductor memory device 21 may be inactivated and the ODT circuit ofthe memory controller 28 may be activated. Accordingly, when the NMOStransistor of the output driver 23 is turned on so that the transmissionline 27 is maintained at a voltage higher than the ground voltage VSSQ(a low level), a standby current may flow through the activated ODTcircuit of the memory controller 28, the transmission line 27, and theturned on NMOS transistor of the output driver 23 to generate DC power.That is, when the voltage of the transmission line 27 is low (when dataon the transmission line 27 is “0”), DC power may be consumed.

The output driver 30 of the memory controller 28 may be an inverter typeof driver including a PMOS transistor and an NMOS transistor or a buffertype of driver. The output driver 30 of the memory controller 28 maydrive the transmission line 27 with the power supply voltage VDDQ or theground voltage VSSQ to transmit data to the input buffer 25 of thesemiconductor memory device 21. When data is transmitted to the inputbuffer 25 of the semiconductor memory device 21, the ODT circuit of thesemiconductor memory device 21 may be activated and the ODT circuit ofthe memory controller 28 may be inactivated. Accordingly, when the NMOStransistor of the output driver 30 of the memory controller 28 is turnedon so that the transmission line 27 is maintained at a voltage higherthan the ground voltage VSSQ (a low level), a standby current may flowthrough the activated ODT circuit of the semiconductor memory device 21,the transmission line 27, and the turned on NMOS transistor of theoutput driver 30 of the memory controller 28 to consume DC power.

The voltage of the transmission line 27 may vary between the powersupply voltage VDDQ (high level) and a voltage higher than the groundvoltage VSSQ (low level) due to the ODT circuits of the of thesemiconductor memory device 21 and the memory controller 28 in PODsignaling. Thus, a data signal swing range in the transmission line 27may be relatively small and the power supply voltage VDDQ may haverelatively little overshoot and/or undershoot because of the ODTcircuits of the semiconductor memory device 21 and the memory controller28 in POD signaling. Accordingly, POD signaling may be used in ahigh-frequency operation of the memory system 20. The high-frequency ofthe memory system 20 may be a frequency greater than or equal to 300MHz. When data is transmitted through the transmission line 27 using PODsignaling, both a DC power component and an AC power component mayexist, and thus POD signaling may consume relatively high power.

FIG. 2 is a table illustrating relationships between operatingfrequencies of the memory systems of FIGS. 1A and 1B and power consumedduring LVCMOS signaling and POD signaling.

In the table of FIG. 2, AC power when data is transmitted through asingle DQ pad may be calculated as follows.

AC power=VDDQ ² *C*F

Here, VDDQ indicates a power supply voltage. C indicates a loadcapacitance at the side of the transmission line 27, viewed from anoutput driver of a semiconductor memory device of the memory system whendata is transmitted from the semiconductor memory device to a memorycontroller of the memory system or a load capacitance at the side of thetransmission line, viewed from an output driver of the memory controllerwhen the data is transmitted from the memory controller to thesemiconductor memory device. F indicates the operating frequency of thememory system.

In the table of FIG. 2, DC power when data is transmitted through asingle DQ pad may be calculated as follows.

DC power=VDDQ ²/(RT+Ron)

Here, VDDQ indicates a power supply voltage, RT indicates a terminationresistance, and Ron indicates an on resistance of an NMOS transistorincluded in the output driver.

In FIG. 2, power is average power when data is transmitted throughthirty-two DQ pads of the memory system at the power supply voltage VDDQof 1.2V. Referring to FIG. 2, both a DC power component and an AC powercomponent may exist in POD signaling and the DC power component may be arelatively large portion of the power consumed during POD signaling. Asignificant DC power component may not exist and substantially only anAC power component may exist in LVCMOS signaling.

A memory system included in a portable device such as a mobile phone maybe required to consume relatively little power. Accordingly, the DCpower component may be reduced in POD signaling and the AC powercomponent may be reduced in LVCMOS signaling to decrease the powerconsumed by a memory system of a portable device.

Furthermore, LVCMOS signaling may be suitable for a low-frequencyoperation of a memory system while POD signaling may be suitable for ahigh-frequency operation of the memory system, as described above.Accordingly, a memory system capable of reducing power consumption andcapable of being used for low-frequency and high-frequency operation maybe needed.

SUMMARY

According to some embodiments of the present invention, a method may beprovided to communicate a plurality of groups of output data bitsrepresenting a respective plurality of groups of input data bits over adata bus wherein each group of output data bits and each group of inputdata bits have an equal data width. Each of the plurality of groups ofinput data bits may be received at a data register. For each group ofinput data bits received at the data register, if a number of data bitsof the group of input data bits having a first logic level is greaterthan half of the data width, the group of input data bits may beinverted, the inverted group of input data bits may be transmitted as arespective group of output data bits in parallel over the data bus, andan inversion flag associated with the respective group of output databits may be transmitted. For each group of input data bits received atthe data register, if a number of data bits of the group of input databits having a second logic level different than the first logic level isgreater than half of the data width, the group of input data bits may betransmitted without inversion as a respective group of output data bitsin parallel over the data bus, and a non-inversion flag associated withthe respective group of output data bits may be transmitted.

According to some other embodiments of the present invention, a methodmay be provided to communicate a plurality of groups of output data bitsrepresenting a respective plurality of groups of input data bits over adata bus wherein each group of output data bits and each group of inputdata bits have an equal data width. Each of the plurality of groups ofinput data bits may be received at a data register. For each group ofinput data bits received at the data register, if a number of data bitsof the group of input data bits that changes with respect to respectivedata bits of a preceding group of output data bits is greater than halfof the data width, the group of input data bits may be inverted, theinverted group of input data bits may be transmitted as a respectivegroup of output data bits in parallel over the data bus, and aninversion flag associated with the respective group of output data bitsmay be transmitted. For each group of input data bits received at thedata register, if a number of data bits of the group of input data bitsthat remains unchanged with respect to respective data bits of apreceding group of output data bits is greater than half of the datawidth, the group of input data bits may be transmitted without inversionas a respective group of output data bits in parallel over the data bus,and a non-inversion flag associated with the respective group of outputdata bits may be transmitted.

According to still other embodiments of the present invention, anelectronic data system may include a data register configured to receiveeach of a plurality of groups of input data bits and an inversioncontroller coupled to the data register. For each group of input databits received at the data register, if a number of data bits of thegroup of input data bits having a first logic level is greater than halfof the data width the inversion controller may be configured to invertthe group of input data bits to generate a respective group of outputdata bits. For each group of input data bits received at the dataregister, if a number of data bits of the group of input data bitshaving a second logic level different than the first logic level isgreater than half of the data width, the inversion controller may beconfigured to generate a respective group of output data bits withoutinversion. An output driver may be coupled to the inversion controllerwith the output driver being configured to transmit each respectivegroup of output data bits in parallel over a data bus. A flag outputgenerator may be coupled to the inversion controller, with the flagoutput generator being configured to transmit an inversion flag witheach group of output data bits generated by inverting the respectivegroup of input data bits, and with the flag output generator beingconfigured to transmit a non-inversion flag with each group of outputdata bits generated without inverting the respective group of input databits.

According to yet other embodiments of the present invention, anelectronic data system may include a data register configured to receiveeach of a plurality of groups of input data bits, and an inversioncontroller coupled to the data register. For each group of input databits received at the data register, if a number of data bits of thegroup of input data bits that changes with respect to respective databits of a preceding group of output data bits is greater than half ofthe data width, the inversion controller may be configured to invert thegroup of input data bits to generate a respective group of output databits. For each group of input data bits received at the data register,if a number of data bits of the group of input data bits that remainsunchanged with respect to respective data bits of a preceding group ofoutput data bits is greater than half of the data width, the inversioncontroller may be configured to generate a respective group of outputdata bits without inversion. An output driver may be coupled to theinversion controller with the output driver being configured to transmiteach respective group of output data bits in parallel over a data bus. Aflag output generator may be coupled to the inversion controller, withthe flag output generator being configured to transmit an inversion flagwith each group of output data bits generated by inverting therespective group of input data bits, and with the flag output generatorbeing configured to transmit a non-inversion flag with each group ofoutput data bits generated without inverting the respective group ofinput data bits.

According to embodiments of the present invention, a semiconductormemory device and/or a memory controller may reduce power consumedand/or may be used for both low-frequency and high-frequency operation.

According to some embodiments of the present invention, a semiconductormemory device may include a first inversion controller generating afirst inversion control signal when the operating frequency of thesemiconductor memory device is less than a reference frequency. A secondinversion controller may generate a second inversion control signal whenthe operating frequency of the semiconductor memory device is greaterthan or equal to the reference frequency. A data inversion/non-inversionunit may invert or non-invert bits of current internal output datacontinuously received from a memory cell array in response to the firstinversion control signal or the second inversion control signal,respectively. The data inversion/non-inversion unit may continuouslyoutput the inverted or non-inverted data as output data. A flag outputunit may generate a flag signal indicating whether the output data isinverted or not in response to the first inversion control signal or thesecond inversion control signal. A data output unit may drive datainput/output pads using LVCMOS signaling based on the output data outputfrom the data inversion/non-inversion unit when the operating frequencyis less than the reference frequency and may drive the data input/outputpads using POD signaling based on the output data output from the datainversion/non-inversion unit when the operating frequency is greaterthan or equal to the reference frequency. The datainversion/non-inversion unit may invert the bits of current internaloutput data in response to the first inversion control signal when thenumber of inverted bits of the current internal output data as comparedwith the corresponding bits of the output data immediately before thecurrent internal output data is greater than half of the data width ofthe current internal output data. The data inversion/non-inversion unitmay invert the bits of the current internal output data in response tothe second inversion control signal when the number of “1” bits or “0”bits of the current internal output data is greater than half of thedata width of the current internal output data.

The first and second inversion controllers may operate in response to afrequency information signal indicating whether the operating frequencyis lower than the reference frequency or not.

According to other embodiments of the present invention, a semiconductormemory device may include first and second inversion controllersrespectively generating first and second inversion control signals inresponse to a frequency information signal indicating operatingfrequency information of the semiconductor memory device. A datainversion/non-inversion unit may invert or non-invert the bits ofcurrent internal output data continuously received from a memory cellarray in response to the first inversion control signal or the secondinversion control signal and may continuously output the inverted ornon-inverted data as output data. A flag output unit may generate a flagsignal indicating whether the output data is inverted or not in responseto the first inversion control signal or the second inversion controlsignal. A data output unit may drive data input/output pads using LVCMOSsignaling corresponding to the first inversion control signal or PODsignaling corresponding to the second inversion control signal based onthe output data output from the data inversion/non-inversion unit inresponse to the frequency information signal. The first inversioncontrol signal may control the data inversion/non-inversion unit toinvert the bits of the current internal output data when the number ofinverted bits of the current internal output data as compared with thecorresponding bits of output data immediately before the currentinternal output data is greater than half of the data width of thecurrent internal output data. The first inversion control signal maycontrol the data inversion/non-inversion unit to non-invert the bits ofthe current internal output data when the number of inverted bits of thecurrent internal output data as compared with the corresponding bits ofthe output data immediately before the current internal output data isless than or equal to half of the data width of the current internaloutput data. The second inversion control signal may control the datainversion/non-inversion unit to invert the bits of the current internaloutput data when the number of “1” bits or “0” bits of the currentinternal output data is greater than half of the data width of thecurrent internal output data. The second inversion control signal maycontrol the data inversion/non-inversion unit to non-invert the bits ofthe current internal output data when the number of “1” bits or “0” bitsof the current internal output data is less than or equal to half of thedata width of the current internal output data.

The frequency information signal may be provided by a memory controllerthrough a mode register set of the semiconductor memory device orthrough a control pad of the semiconductor memory device. Thesemiconductor memory device may further include a read circuit reading aplurality of internal output data stored in the memory cell array inparallel, and the read circuit may include a data register storing theplurality of internal output data read in parallel and may continuouslyoutput the current internal output data to the datainversion/non-inversion unit.

The first inversion controller may include a switch and first and secondcomparators. The switch may output the current internal output dataoutput from the data register in response to the frequency informationsignal. The first comparator may compare the bits of current internaloutput data output from the switch with the corresponding bits of outputdata immediately before the current internal output data, counting thenumber of inverted bits of the current internal output data compared tothe bits of the output data immediately before the current internaloutput data and outputting a count value corresponding to the countingresult. The second comparator may compare the count value with half ofthe data width of the current internal output data and may output thefirst inversion control signal having a first logic level, whichcontrols the data inversion/non-inversion unit to invert the currentinternal output data, when the count value is greater than half of thedata width of the current internal output data.

The second inversion controller may include a switch, a counter, and acomparator. The switch may output the current internal output dataoutput from the data register in response to the frequency informationsignal. The counter may count the number of “1” bits of the currentinternal output data and may output a count value corresponding to thecounting result when an output driver used for POD signaling is aninverter type of driver, and may count the number of “0” bits of thecurrent internal output data and may output a count value correspondingto the counting result when the output driver is a buffer type ofdriver. The comparator may compare the count value to half of the datawidth of the current internal output data and may output the secondinversion control signal having a first logic level, which controls thedata inversion/non-inversion unit to invert the current internal outputdata, when the count value is greater than half of the data width of thecurrent internal output data.

The flag output unit may include a switch and a flag buffer. The switchmay output the first inversion control signal or the second inversioncontrol signal in response to the frequency information signal. The flagbuffer may output the flag signal to a flag pad in response to the firstinversion control signal or the second inversion control signal outputrespectively from the switch.

The data output unit may include an output buffer, first and secondoutput driver units, and a switch. The output buffer unit may buffer theoutput data output from the data inversion/non-inversion unit. The firstoutput driver unit may drive the data input/output pads using LVCMOSsignaling. The second output driver unit may drive the data input/outputpads using POD signaling. The switch may output the output data outputfrom the output buffer unit to the first output driver unit or thesecond output driver unit in response to the frequency informationsignal.

According to other embodiments of the present invention, a memorycontroller may include a first inversion control signal when theoperating frequency of the memory controller is lower than a referencefrequency. A second inversion controller may generate a second inversioncontrol signal when the operating frequency is higher than or equal tothe reference frequency. A data inversion/non-inversion unit may invertor non-invert the bits of current internal input data continuouslyreceived from a data register in response to the first inversion controlsignal or the second inversion control signal and may continuouslyoutput the inverted or non-inverted data as input data. A flag outputunit may output a flag signal indicating whether the input data isinverted or not in response to the first inversion control signal or thesecond inversion control signal. A data output unit may drive datainput/output pads connected to a semiconductor memory device usingLVCMOS signaling based on the input data output from the datainversion/non-inversion unit when the operating frequency is lower thanthe reference frequency and may drive the data input/output pads usingPOD signaling based on the input data output from the datainversion/non-inversion unit when the operating frequency is higher thanor equal to the reference frequency. The data inversion/non-inversionunit may invert the bits of the current internal input data in responseto the first inversion control signal when the number of inverted bitsof the current internal input data as compared with the correspondingbits of the input data immediately before the current internal inputdata is greater than half of the data width of the current internalinput data. The data inversion/non-inversion unit may invert the bits ofthe current internal input data in response to the second inversioncontrol signal when the number of “1” bits or “0” bits of the currentinternal input data is greater than half of the data width of thecurrent internal input data.

The first and second inversion controllers may operate in response to afrequency information signal indicating whether the operating frequencyis lower than the reference frequency or not.

According to other embodiments of the present invention, a memorycontroller may include first and second inversion controllersrespectively generating first and second inversion control signals inresponse to a frequency information signal indicating operatingfrequency information of the memory controller. A datainversion/non-inversion unit may invert or non-invert the bits ofcurrent internal input data continuously received from a data registerin response to the first inversion control signal or the secondinversion control signal and may continuously output the inverted ornon-inverted data as input data. A flag output unit may output a flagsignal indicating whether the input data is inverted or not in responseto the first inversion control signal or the second inversion controlsignal. A data output unit may drive data input/output pads connected toa semiconductor memory device using LVCMOS signaling corresponding tothe first inversion control signal or POD signaling corresponding to thesecond inversion control signal based on the input data output from thedata inversion/non-inversion unit, in response to the frequencyinformation signal. The first inversion control signal may control thedata inversion/non-inversion unit to invert the bits of the currentinternal input data when the number of inverted bits of the currentinternal input data as compared with the corresponding bits of the inputdata right before the current internal input data is greater than halfof the data width of the current internal input data. The firstinversion control signal may control the data inversion/non-inversionunit to non-invert the bits of the current internal input data when thenumber of inverted bits of the current internal input data as comparedwith the corresponding bits of the input data immediately before thecurrent internal input data is less than or equal to half of the datawidth of the current internal input data. The second inversion controlsignal may control the data inversion/non-inversion unit to invert thebits of the current internal input data when the number of “1” bits or“0” bits of the current internal input data is greater than half of thedata width of the current internal input data. The second inversioncontrol signal may control the data inversion/non-inversion unit tonon-invert the bits of the current internal input data when the numberof “1” bits or “0” bits of the current internal input data is less thanor equal to half of the data width of the current internal input data.

According to other embodiments of the present invention, a memory systemmay include a semiconductor memory device and a memory controllercontrolling a data read operation of the semiconductor memory device.The semiconductor memory device may perform the data read operation byinverting the bits of current internal output data continuously readfrom a memory cell array when the number of inverted bits of the currentinternal output data as compared with the corresponding bits of outputdata immediately before the current internal output data is greater thanhalf of the data width of the current internal output data, outputtingthe inverted data as the output data, transmitting the output data tothe memory controller through data buses using LVCMOS signaling and,simultaneously, transmitting a flag signal indicating inversion of theoutput data to the memory controller when the operating frequency of thememory system is lower than a reference frequency. The semiconductormemory device may perform the data read operation by inverting the bitsof the current internal output data when the number of “1” bits or “0”bits of the current internal output data is greater than half of thedata width of the current internal output data, outputting the inverteddata as output data, transmitting the output data to the memorycontroller through data buses using POD signaling and, simultaneously,transmitting the flag signal indicating inversion of the output data tothe memory controller when the operating frequency of the memory systemis higher than or equal to the reference frequency.

The semiconductor memory device may operate in response to a frequencyinformation signal indicating whether the operating frequency is lowerthan the reference frequency or not, and the frequency informationsignal may be provided by the memory controller.

According to other embodiments of the present invention, a memory systemmay include a semiconductor memory device and a memory controllercontrolling a data write operation of the semiconductor memory device.The memory controller may perform the data write operation by invertingthe bits of current internal input data continuously read from a dataregister when the number of inverted bits of the current internal inputdata as compared with the corresponding bits of input data immediatelybefore the current internal input data is greater than half of the datawidth of the current internal input data, outputting the inverted dataas the input data, transmitting the input data to the semiconductormemory device through data buses using LVCMOS signaling and,simultaneously, transmitting a flag signal indicating inversion of theinput data to the semiconductor memory device when the operatingfrequency of the memory system is lower than a reference frequency. Thememory controller may perform the data write operation by inverting thebits of the current internal input data when the number of “1” bits or“0” bits of the current internal input data is greater than half of thedata width of the current internal input data, outputting the inverteddata as input data, transmitting the input data to the semiconductormemory device through the data buses using POD signaling and,simultaneously, transmitting the flag signal indicating inversion of theinput data to the semiconductor memory device when the operatingfrequency of the memory system is greater than or equal to the referencefrequency.

The memory controller may operate in response to a frequency informationsignal indicating whether the operating frequency is lower than thereference frequency or not.

Memory systems according to embodiments of the present invention mayselectively use LVCMOS signaling suitable for a low-frequency operationand POD signaling suitable for a high-frequency operation. Furthermore,the memory system may reduce AC power in LVCMOS signaling using a datainversion method suitable for LVCMOS signaling and may decrease DC powerin POD signaling using a data inversion method suitable for PODsignaling.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other features and advantages of the present inventionwill become more apparent by describing in detail embodiments thereofwith reference to the attached drawings in which:

FIG. 1A illustrates a memory system using low voltage complimentarymetal oxide semiconductor (LVCMOS) signaling.

FIG. 1B illustrates a memory system using pseudo open drain (POD)signaling.

FIG. 2 is a table illustrating power consumed for LVCMOS signaling andpower consumed for POD signaling with respect to the operating frequencyof memory systems of FIGS. 1A and 1B.

FIG. 3 is a block diagram illustrating a semiconductor memory deviceaccording to some embodiments of the present invention.

FIG. 4 is a flow chart illustrating a data inversion methods for LVCMOSsignaling according to some embodiments of the present invention.

FIG. 5A illustrates output data and flag signals according to datainversion methods illustrated in FIG. 4, according to some embodimentsof the present invention.

FIG. 5B is a timing diagram of output data and flag signals illustratedin FIG. 5A, according to some embodiments of the present invention.

FIG. 6 is a flow chart illustrating data inversion methods for PODsignaling according to some embodiments of the present invention.

FIG. 7A illustrates output data and flag signals according to datainversion methods illustrated in FIG. 6 according to some embodiments ofthe present invention.

FIG. 7B is a timing diagram of output data and flag signals illustratedin FIG. 7A according to some embodiments of the present invention.

FIG. 8 is a graph illustrating a reduction in power consumed by PODsignaling using data inversion methods illustrated in FIG. 6 and areduction in power consumed by LVCMOS signaling using data inversionmethods illustrated in FIG. 4, according to some embodiments of thepresent invention.

FIG. 9 is a block diagram of a memory controller according to someembodiments of the present invention.

FIG. 10 is a block diagram of a memory system according to someembodiments of the present invention.

DETAILED DESCRIPTION

The present invention is described more fully hereinafter with referenceto the accompanying drawings, in which example embodiments of theinvention are shown. The present invention may, however, be embodied inmany different forms and should not be construed as limited to theexample embodiments set forth herein. Rather, these example embodimentsare provided so that this disclosure will be thorough and complete, andwill fully convey the scope of the present invention to those skilled inthe art. Moreover, each embodiment described and illustrated hereinincludes its complementary conductivity type embodiment as well.

It will be understood that when an element is referred to as being“connected to,” “coupled to” or “responsive to” (and/or variantsthereof) another element, it can be directly connected, coupled orresponsive to the other element or intervening elements may be present.In contrast, when an element is referred to as being “directly connectedto,” “directly coupled to” or “directly responsive to” (and/or variantsthereof) another element, there are no intervening elements present.Like numbers refer to like elements throughout. As used herein, the term“and/or” includes any and all combinations of one or more of theassociated listed items and may be abbreviated as “/”.

It will be understood that, although the terms first, second, third,etc. may be used herein to describe various elements, components,regions, layers and/or sections, these elements, components, regions,layers and/or sections should not be limited by these terms. These termsare only used to distinguish one element, component, region, layer orsection from another region, layer or section. Thus, a first element,component, region, layer or section discussed below could be termed asecond element, component, region, layer or section without departingfrom the teachings of the present invention.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the invention. Asused herein, the singular forms “a,” “an” and “the” are intended toinclude the plural forms as well, unless the context clearly indicatesotherwise. It will be further understood that the terms “comprises”and/or “comprising” (and/or variants thereof), when used in thisspecification, specify the presence of stated features, integers, steps,operations, elements, and/or components, but do not preclude thepresence or addition of one or more other features, integers, steps,operations, elements, components, and/or groups thereof. In contrast,the term “consisting of” (and/or variants thereof) when used in thisspecification, specifies the stated number of features, integers, steps,operations, elements, and/or components, and precludes additionalfeatures, integers, steps, operations, elements, and/or components.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art to which the present invention belongs. Itwill be further understood that terms, such as those defined in commonlyused dictionaries, should be interpreted as having a meaning that isconsistent with their meaning in the context of the relevant art and thepresent application, and will not be interpreted in an idealized oroverly formal sense unless expressly so defined herein.

FIG. 3 is a block diagram illustrating a semiconductor memory device 100according to some embodiments of the present invention. Referring toFIG. 3, the semiconductor memory device 100 may include a memory cellarray 102, a read circuit 104, a first inversion controller 108, asecond inversion controller 116, a data inversion/non-inversion unit124, a flag output unit 126, a data output unit 134, an input bufferunit 146, a write circuit 148, a mode register set unit 150, and acommand decoder 152.

The memory cell array 102 includes a plurality of memory cells storingdata. The read circuit 104 includes a data register 106 and a data readoperation circuit of the semiconductor memory device 100 (for example,an output sense amplifier).

The read circuit 104 may perform a burst read operation that reads apredetermined number of internal output data DOI stored in the memorycell array 102 in parallel (or simultaneously) in response to a readsignal (READ) and a burst length signal (BL) and may store the internaloutput data (DOI) read in parallel in the data register 106. Forexample, the data width of the DOI data may be x8 and the number of DOIdata read in parallel may be 4 when the BL signal indicates 4. The DOIdata stored in the data register 106 may be continuously (orsequentially) output to the data inversion/non-inversion unit 124.

The first inversion controller 108 may generate a first inversioncontrol signal (INV1) to control whether the DOI data that iscontinuously input to the data inversion/non-inversion unit 124 isinverted or not when the operating frequency of the semiconductor memorydevice 100 is less than a reference frequency (for example, 300 MHz) oris a low operating frequency.

The first inversion controller 108 that is used for a low-frequencyoperation of the semiconductor memory device 100 may generate the INV1signal in response to a frequency information signal (FI) indicatingoperating frequency information of the semiconductor memory device 100.

The FI signal may indicate whether the operating frequency of thesemiconductor memory device 100 is a high operating frequency (i.e., afrequency greater than or equal to the reference frequency) or the lowoperating frequency (i.e., a frequency less than the referencefrequency). For example, the logic level of the FI signal may be highwhen the operating frequency is a relatively low operating frequency,and the logic level of the FI signal may be low when the operatingfrequency is a relatively high operating frequency. The FI signal may beprovided by a memory controller (not shown) through the mode registerset unit 150 or through a control pad (not shown) of the semiconductormemory device 100.

The second inversion controller 116 may generate a second inversioncontrol signal (INV2) to control whether the DOI data continuously inputto the data inversion/non-inversion unit 124 is inverted or not when theoperating frequency of the semiconductor memory device 100 is greaterthan the reference frequency. The second inversion controller 116 thatis used for high-frequency operation of the semiconductor memory device100 may generate the INV2 signal in response to the FI signal.

The data inversion/non-inversion unit 124 may invert or non-invert thebits of the current DOI data that are continuously received from thememory cell array 102 through the data register 106 in response to theINV1 signal and/or the INV2 signal, and may continuously output theinverted or non-inverted DOI data as output data DO.

The INV1 signal of the first inversion controller 108 may control thedata inversion/non-inversion unit 124 to invert the current DOI datawhen the number of inverted bits of the current DOI data as comparedwith the corresponding bits of the output data DO immediately before thecurrent DOI data (that is, the previous output data DO) is greater thanhalf of the data width of the current DOI data. The INV1 signal maycontrol the data inversion/non-inversion unit 124 to non-invert thecurrent DOI data when the number of inverted bits of the current DOIdata as compared with the corresponding bits of the output data DOimmediately before the current DOI data is less than or equal to half ofthe data width of the current DOI data.

The first inversion controller 108 may include a first switch 110, afirst comparator 112 and a second comparator 114. The first inversioncontroller 108 corresponds to a first output driver unit 140 that drivesdata input/output pads (DQ pads) 144 connected to transmission lines 16(as illustrated for example, in FIG. 1A according to LVCMOS signaling)and may use a data inversion scheme for LVCMOS signaling. LVCMOSsignaling is a transmission line driving method carried out by an outputdriver of a semiconductor memory device, as described above, forexample, with reference to FIG. 1A.

The first switch 110 outputs the current DOI data received from the dataregister 106 in response to the FI signal. The first comparator 112compares the bits of the current DOI data output from the first switch110 with the corresponding bits of the output data DO immediatelypreceding the current DOI data, counts the number of inverted bits ofthe current DOI data as compared with the corresponding bits of theprevious output data DO immediately preceding the current DOI data, andoutputs a first count value corresponding to the counting result.

The second comparator 114 compares the first count value with half ofthe data width of the current DOI data. The second comparator 114outputs the INV1 signal having a first logic level (for example, a highlevel) to control the current DOI data to be inverted when the firstcount value is greater than half of the data width of the current DOIdata. The second comparator 114 outputs INV1 signal having a secondlogic level (for example, a low level) to control the current DOI datato be non-inverted when the first count value is less than or equal tohalf of the data width of the current DOI data.

Accordingly, when the semiconductor memory device 100 uses LVCMOSsignaling, the first inversion controller 108 may control the number ofbits of output data DO, which are inverted (toggled) on transmissionline, to be less than or equal to half of the data width of the DOI datato reduce AC power during LVCMOS signaling.

The INV2 signal of the second inversion controller 116 may control thedata inversion/non-inversion unit 124 to invert the current DOI datawhen the number of “1” bits or “0” bits included in the current DOI datais greater than half of the data width of the current DOI data. The INV2signal controls the data inversion/non-inversion unit 124 to non-invertthe current DOI data when the number of “1” bits or “0” bits included inthe current DOI data is less than or equal to half of the data width ofthe current DOI data.

The second inversion controller 116 includes a second switch 118, acounter 120 and a third comparator 122. The second inversion controller116 corresponds to a second output driver unit 142 of the data outputunit 134 that drives the DQ pads 144 connected to transmission lines 27(as illustrated, for example, in FIG. 1B according to POD signaling) andmay use a data inversion scheme for POD signaling. POD signaling is atransmission line driving method carried out by an output driver of asemiconductor memory device, as described above, for example, withreference to FIG. 1B.

The second switch 118 may output the current DOI data received from thedata register 106 in response to the FI signal. The counter 120 countsthe number of “1” bits or “0” bits included in the current DOI data andoutputs a second count value corresponding to the counting result. Whenan output driver (such as the output driver 23 illustrated in FIG. 1B)included in the second output driver unit 142 corresponding to thesecond inversion controller 116 is an inverter type of driver, thecounter 120 may count the number of “1” bits of the current DOI data.When the output driver included in the second output driver unit 142corresponding to the second inversion controller 116 is a buffer type ofdriver, the counter 120 may count the number of “0” bits of the currentDOI data.

The third comparator 122 may compare the second count value with half ofthe data width of the current DOI data. The third comparator 122 mayoutput the INV2 signal having a first logic level (for example, a highlevel) to control the current DOI data to be inverted when the secondcount value is greater than half of the data width of the current DOIdata. The third comparator 122 may output the INV2 signal having asecond logic level (for example, a low level) to control the current DOIdata to be non-inverted when the second count value is less than orequal to half of the data width of the current DOI data.

Accordingly, when the semiconductor memory device 100 uses PODsignaling, the second inversion controller 116 may control the number of“0” bits on the transmission line to be less than or equal to half ofthe data width of the DOI data to reduce the DC power in POD signaling.

The flag output unit 126 may output a flag signal (FLAG) indicatingwhether the output data DO is inverted or not to a memory controller(not shown) in response to the INV1 signal or the INV2 signal. Forexample, the FLAG signal may indicate that the output data DO isinverted when the FLAG signal has a high level (that is, data “1”) andmay indicate that the output data DO has not been inverted when it has alow level (that is, data “0”).

The flag output unit 126 may include a third switch 128, a flag buffer130 and a flag pad 132. The third switch 128 may output the INV1 signalor the INV2 signal in response to the FI signal. The flag buffer 130 mayoutput the FLAG signal to the flag pad 132 in response to the INV1signal or the INV2 signal output from the third switch 128.

The data output unit 134 may drive the DQ pads 144 according to LVCMOSsignaling based on the output data DO continuously output from the datainversion/non-inversion unit 124 when the operating frequency of thesemiconductor memory device 100 is a low operating frequency. The dataoutput unit 134 may drive the DQ pads 144 according to POD signalingbased on the output data DO output from the data inversion/non-inversionunit 124 when the operating frequency of the semiconductor memory device100 is a high operating frequency.

The data output unit 134 may include an output buffer unit 136, a fourthswitch 138, the first output driver unit 140, the second output driverunit 142, and the DQ pads 144 connected to the memory controller (notshown) through transmission lines (not shown).

The output buffer unit 136 buffers the output data DO output from thedata inversion/non-inversion unit 124 and outputs the buffered data tothe fourth switch 138. The data output from the output buffer unit 136is synchronized with a clock signal (CLK). When the data width of theoutput data DO output from the data inversion/non-inversion unit 124 isx8, for example, the output buffer unit 136 may include eight outputbuffers corresponding to the data width of the output data DO.

The fourth switch 138 may selectively output the data output from theoutput buffer unit 136 to the first output driver unit 140 or to thesecond output driver unit 142 in response to the FI signal.

The first output driver unit 140 (corresponding to the first inversioncontroller 108) may receive the output data from the fourth switch 138and may drive the DQ pads 144 with LVCMOS signaling. The first outputdriver unit 140 may include an output driver (such as an output driver13 as illustrated, for example, in FIG. 1A). When the data width of theoutput data DO is x8, for example, the first output driver unit 140 maycorrespondingly include eight output drivers (as the output driver 13illustrated in FIG. 1A).

The second output driver unit 142 (corresponding to the second inversioncontroller 116) may receive the output data from the fourth switch 138and may drive the DQ pads 144 with POD signaling. The second outputdriver unit 142 may include a circuit (such as the output driver 23 andthe termination circuit that are illustrated, for example, in FIG. 1B).When the data width of the output data DO is x8, for example, the secondoutput driver unit 142 may correspondingly include eight circuits eachincluding a respective output driver 23 and termination circuit.

Accordingly, the semiconductor memory device 100 may selectively useLVCMOS signaling for low-frequency operation and POD signaling forhigh-frequency operation.

The input buffer unit 146 may buffer input data DI continuouslytransmitted from the memory controller and may output the buffered inputdata to the write circuit 148. When the data width of the input data DIis x8, for example, the input buffer unit 146 may include eight inputbuffers corresponding to the data width of the input data DI.

The write circuit 148 may include a circuit related to a data writeoperation of the semiconductor memory device 100 (for example, an inputdriver). The write circuit 148 may perform a burst write operation thatwrites input data DI output from the input buffer unit 146 in parallelto the memory cell array 102 in response to a write signal (WRITE). Thenumber of input data DI written in parallel may be 4.

The mode register set 150 may generate the FI signal and the BL signalin response to an address signal (ADDR) provided by the memorycontroller. The command decoder 152 may generate the READ signal and theWRITE signal synchronized with the CLK signal in response to a commandsignal (CMD) provided by the memory controller.

As described above, the semiconductor memory device 10 according to someembodiments of the present invention may selectively use LVCMOSsignaling for a low-frequency operation and POD signaling for ahigh-frequency operation. Furthermore, the semiconductor memory device10 may reduce AC power during LVCMOS signaling using a data inversionscheme suitable for LVCMOS signaling and may decrease DC power duringPOD signaling using a data inversion scheme suitable for POD signaling.

FIG. 4 is a flow chart illustrating a data inversion method 200 forLVCMOS signaling according to some embodiments of the present invention.The data inversion method 200 will be explained with reference to FIGS.3 and 4.

The data inversion method 200 for LVCMOS signaling used for alow-frequency operation of the semiconductor memory device 100 may becarried out using the first inversion controller 108, the datainversion/non-inversion unit 124, the flag output unit 126 and the dataoutput unit 134.

In the receiving operation 205, the data inversion/non-inversion unit124 and the first inversion controller 108 may receive current DOI datafrom the data register 106. In the first comparison operation 210, thefirst comparator 112 of the first inversion controller 108 compares thebits of the current DOI data with the corresponding bits of the outputdata DO immediately preceding the current DOI data, counts the number ofinverted bits of the current DOI data as compared with the correspondingbits of the output data DO immediately preceding the current DOI data,and outputs the first count value corresponding to the counting result.

In the second comparison operation 215, the second comparator 114 of thefirst inversion controller 108 compares the first count value with halfof the data width of the current DOI data. When the first count value isless than or equal to half of the data width of the current DOI data,the data inversion method 200 proceeds to the non-inversion operation220. When the first count value is greater than half of the data widthof the current DOI data in the second comparison operation 215, the datainversion method 200 proceeds to the inversion operation 225.

In the non-inversion operation 220, the flag buffer 130 sets the FLAGsignal to a data value of ‘0’ to indicate non-inversion of the outputdata DO, and the data inversion/non-inversion unit 124 non-inverts thecurrent DOI data and outputs the non-inverted data as the output dataDO.

In the inversion operation 225, the flag buffer 130 sets the FLAG signalto a data value of ‘1’ to indicate inversion of the output data DO, andthe data inversion/non-inversion unit 124 inverts the current DOI dataand outputs the inverted data as the output data DO.

In the confirmation operation 230, whether the current DOI data istransmitted from the data register 106 to the datainversion/non-inversion unit 124 and the first inversion controller 108is confirmed. That is, whether the burst read operation that readsinternal output data in parallel from the memory cell array 102 isfinished is confirmed.

When it is confirmed that the burst read operation is not finished inthe confirmation operation 230, the data inversion method 200 returns tothe receiving operation 205. When it is confirmed that the burst readoperation is finished in the confirmation operation 230, the datainversion method 200 is completed.

FIG. 5A illustrates output data DO and the FLAG signal according to thedata inversion method illustrated in FIG. 4, and FIG. 5B is a timingdiagram of the output data DO and the FLAG signal, according toembodiments of the present invention. FIG. 5A illustrates the outputdata DO and the FLAG signal when the data width of the DOI data is x8and the burst length of the DOI data is 4. Referring to FIGS. 3 and 5A,four units of internal output data DOI1, DOI2, DOI3 and DOI4 (eachincluding 8 bits) that are read in parallel from the memory cell array102 are sequentially output by the data register 106 to the datainversion/non-inversion unit 124.

The first internal output data unit DOI1, “00000000”, received by thedata inversion/non-inversion unit 124 is compared with the output dataDO (not shown) (for example, “00000001”) immediately preceding the firstinternal output data DOI1 bit by bit. Hence, the number of inverted(toggled) bits of the first internal output data DOI1 is compared withthe corresponding bits of the previous output data. Since the number ofinverted bits of the first internal output data DOI1 relative to theimmediately preceding output data (i.e., 1) is less than half of thedata width of the DOI data, 4, the first internal output data unit DOI1is not inverted and “00000000” is output as first output data DO1. TheFLAG signal corresponding to the first output data DO1 has a data valueof “0” because the first output data DO1 has not been inverted.

The second internal output data DOI2, “11100110”, received by the datainversion/non-inversion unit 124 is compared with the first output dataDO1, “00000000”, immediately preceding the second internal output dataDOI2, bit by bit. Hence, the number of inverted bits of the secondinternal output data DOI2 compared to the corresponding bits of thefirst output data DO1 is 5. Since the number of inverted bits of thesecond internal output data DO2 (relative to output data DO1) is greaterthan half of the data width of the internal output data DOI, 4, thesecond internal output data DOI2 is inverted so that “00011001” isoutput as second output data DO2. The FLAG signal corresponding to thesecond output data DO2 has a data value of “1” because the secondinternal output data unit DO2 was inverted.

The third internal output data DOI3 and the fourth internal output dataDOI4 are inverted or non-inverted according to the same data inversionmethod as previously described so that repetitive explanations thereofare omitted.

Referring to FIG. 5B, the READ signal that dictates the burst readoperation is synchronized with the CLK signal and both may be applied tothe semiconductor memory device 100 (illustrated in FIG. 3) such as adouble data rate synchronous DRAM from a memory controller. Then, thefirst to fourth output data DO1, DO2, DO3 and DO4 and the FLAG signalsmay be continuously output in synchronization with a falling edge and arising edge of the CLK signal.

FIG. 6 is a flow chart of a data inversion method 300 for POD signalingaccording to embodiments of the present invention. The data inversionmethod 300 will be explained with reference to FIGS. 3 and 6.

The data inversion method 300 for POD signaling used for ahigh-frequency operation of the semiconductor memory device 100 may beexecuted by the second inversion controller 116, the datainversion/non-inversion unit 124, the flag output unit 126 and the dataoutput unit 134.

In the receiving operation 305, the data inversion/non-inversion unit124 and the second inversion controller 116 receive the current DOI datafrom the data register 106. In the counting operation 310, the counter120 of the second inversion controller 116 counts the number of databits having a value “1” or the number of data bits having a value “0”included in the current DOI data and outputs the second count valuecorresponding to the counting result.

In the comparison operation 315, the third comparator 122 of the secondinversion controller 116 compares the second count value with half ofthe data width of the current DOI data. When the second count value isless than or equal to half of the data width of the current DOI data,the data inversion method 300 proceeds to the non-inversion operation320. When the second count value is greater than half of the data widthof the current DOI data in the comparison operation 315, the datainversion method 300 proceeds to the inversion operation 325.

In the non-inversion operation 320, the flag buffer 130 sets the FLAGsignal to a data value of ‘0’ that indicates a non-inversion of theoutput data DO, and the data inversion/non-inversion unit 124non-inverts the current DOI data and outputs the non-inverted data asthe output data DO.

In the inversion operation 325, the flag buffer 130 sets the FLAG signalto a data value of ‘1’ that indicates an inversion of the output dataDO, and the data inversion/non-inversion unit 124 inverts the currentDOI data and outputs the inverted data as the output data DO.

In the confirmation operation 330, whether the current DOI data aretransmitted from the data register 106 to the datainversion/non-inversion unit 124 and the second inversion controller 116is confirmed. That is, whether the burst read operation that readsinternal output data in parallel from the memory cell array 102 isfinished is confirmed.

When it is confirmed that the burst read operation is not finished inconfirmation operation 330, the data inversion method 300 returns to thereceiving operation 305. When it is confirmed that the burst readoperation is finished in the confirmation operation 330, the datainversion method 300 is completed.

FIG. 7A illustrates the output data DO and the FLAG signal according tothe data inversion method 300 illustrated in FIG. 6, and FIG. 7B is atiming diagram of the output data DO and the FLAG signal, according toembodiments of the present invention. FIG. 7A illustrates the outputdata DO and the FLAG signal when the data width of the DOI data units isx8 and the burst length of the DOI data is 4. Referring to FIGS. 3 and7A, four internal output data units DOI1, DOI2, DOI3 and DOI4 that areread in parallel from the memory cell array 102 are sequentially outputby the data register 106 to the data inversion/non-inversion unit 124.

The number of “0” bits of the first internal output data unit DOI1,“00000000”, received by the data inversion/non-inversion unit 124 iscounted. Hence, the number of “0” bits of the first internal output dataDOI1 is 8. Since the number of “0” bits of the first internal outputdata unit DOI1 is greater than half of the data width of the DOI data,4, the first internal output data DOI1 is inverted and “11111111” isoutput as first output data DO1. The FLAG signal corresponding to thefirst output data DO1 has a data value of “1” because the first outputdata DO1 is inverted.

The number of “0” bits of the second internal output data DOI2,“11100110”, received by the data inversion/non-inversion unit 124 iscounted. Hence, the number of “0” bits of the second internal outputdata DOI2 is 3. Since the number of “0” bits of the second internaloutput data DOI2 is less than half of the data width of the DOI data, 4,the second internal output data DOI2 is not inverted and “11100110” isoutput as second output data DO2. The FLAG signal corresponding to thesecond output data DO2 has a data value of “0” because the second outputdata DO2 is not inverted.

The third internal output data DOI3 and the fourth internal output dataDOI4 are inverted or non-inverted according to the same data inversionmethod as described above so that explanations thereof are omitted.

Referring to FIG. 7B, the READ signal that dictates the burst readoperation is synchronized with the CLK signal and both may be applied tothe semiconductor memory device 100 (illustrated in FIG. 3) such as adouble data rate synchronous DRAM. Then, the first to fourth output dataDO1, DO2, DO3 and DO4 and the FLAG signals are continuously output insynchronization with falling and/or rising edges of the CLK signal.

FIG. 8 is a graph illustrating reductions in power consumed during PODsignaling using the data inversion method 300 illustrated in FIG. 6 andreductions in power consumed during LVCMOS signaling using the datainversion method 200 illustrated in FIG. 4, according to someembodiments of the present invention.

Referring to FIG. 8, line “A” indicates power consumed as a function ofoperating frequency during POD signaling using a no data inversionmethod, and line “B” indicates power consumed as a function of operatingfrequency during POD signaling using the data inversion method 300according to embodiments of the present invention. In addition, line “C”indicates power consumed as a function of operating frequency duringLVCMOS signaling using a no data inversion method, and line “D”indicates power consumed as a function of operating frequency during PODsignaling using the data inversion method 200 according to embodimentsof the present invention. In FIG. 8, consumed power is average powerwhen data is transmitted through 32 DQ pads at the power supply voltageVDDQ of 1.2V.

Referring to lines “A” and “B”, it can be seen that POD signaling usingthe data inversion method 300 according to embodiments of the presentinvention may reduce consumed power by approximately 18% as comparedwith POD signaling without using the data inversion method, and LCVMOSsignaling using the data inversion method 200 according to embodimentsof the present invention may reduce consumed power by approximately 22%as compared with LVCMOS signaling without using the data inversionmethod.

FIG. 9 is a block diagram illustrating a memory controller 400 accordingto some additional embodiment is of the present invention. Referring toFIG. 9, the memory controller 400 includes a data register 402, a firstinversion controller 404, a second inversion controller 412, a datainversion/non-inversion unit 420, a flag output unit 422, a data outputunit 430, an input buffer unit 442, and a command output unit 444. Thememory controller 400 may control data write and/or data read operationsof a semiconductor memory device, such as the semiconductor memorydevice 100 of FIG. 3.

The first inversion controller 404 may include a first switch 406, afirst comparator 408 and a second comparator 410. The second inversioncontroller 412 may include a second switch 414, a counter 416 and athird comparator 418.

The flag output unit 422 may include a third switch 424, a flag buffer426 and a flag pad 428 connected to the semiconductor memory device (notshown) through a transmission line (not shown). The data output unit 430may include an output buffer unit 432, a fourth switch 434, a firstoutput driver unit 436, a second output driver unit 438, and DQ pads 440connected to the semiconductor memory device through transmission lines.

The first inversion controller 404, the second inversion controller 412,the flag output unit 422 and the data output unit 430 may besubstantially identical to the first inversion controller 108, thesecond inversion controller 116, the flag output unit 126 and the dataoutput unit 134 respectively illustrated in FIG. 3 so that explanationsthereof are omitted. The first inversion controller 404, the secondinversion controller 412, the flag output unit 422 and the data outputunit 430 may operate in response to an FI signal that indicatesoperating frequency information of the memory controller 400. The FIsignal may be provided by a central processing unit external to thememory controller 40.

Furthermore, operations of the data inversion/non-inversion unit 420(controlled by the first inversion controller 404 and the secondinversion controller 412) and the data register 402, which continuouslyoutputs internal input data DII to the data inversion/non-inversion unit420 may be substantially identical to those of the datainversion/non-inversion unit 124 and the data register 106 respectivelyillustrated in FIG. 3 so that explanations thereof are omitted. However,data output from the data inversion/non-inversion unit 420 may be inputdata DI for data write operations of the semiconductor memory devicewhile data output from the data inversion/non-inversion unit 124illustrated in FIG. 3 may be output data DO for data read operations ofthe semiconductor memory device. Furthermore, the internal input dataDII stored in the data register 402 may be provided by the centralprocessing unit while the internal output data DOI stored in the dataregister 106 illustrated in FIG. 3 may be provided by the memory cellarray 102.

The input buffer unit 442 may buffer output data DO continuouslytransmitted from the semiconductor memory device. The buffered outputdata DO may be used in a circuit block included in the memory controller400 or input to an external cache memory or the central processing unit.When the data width of the output data DO is x8, for example, the inputbuffer unit 442 may include eight input buffers corresponding to thedata width of the output data DO.

The command output unit 444 provides the command signal (CMD) to thesemiconductor memory device in response to a signal input from thecentral processing unit.

The memory controller 400 according to some embodiments of the presentinvention may selectively use LVCMOS signaling for low-frequencyoperations and POD signaling for high-frequency operations whentransmitting input data for write operations to the semiconductor memorydevice. Furthermore, the memory controller 400 may reduce AC power inLVCMOS signaling using a data inversion method suitable for LVCMOSsignaling and may reduce DC power in POD signaling using a datainversion method suitable for POD signaling.

FIG. 10 is a block diagram of a memory system 500 according to someembodiments of the present invention. The memory system 500 may includethe semiconductor memory device 100 illustrated in FIG. 3 and the memorycontroller 400 illustrated in FIG. 9.

The memory controller 400 may provide the CMD signal and the FI signalto the semiconductor memory device 100. The semiconductor memory device100 may operate in response to the FI signal that indicates whether theoperating frequency of the memory system 500 is greater than or lessthan the reference frequency, that is, whether the operating frequencyof the memory system 500 is a relatively high operating frequency or arelatively low operating frequency. The memory controller 400 mayoperate in response to the FI signal.

The data read operation of the semiconductor memory device 100 will beexplained. When the operating frequency of the memory system 500 is arelatively low operating frequency, the semiconductor memory device 100may invert current internal output data continuously read from thememory cell array 102 illustrated in FIG. 3 and may output the inverteddata as output data (DATA) when the number of inverted bits of thecurrent internal output data as compared with the corresponding bits ofoutput data immediately preceding the current internal output data isgreater than half of the data width of the current internal output data.In addition, the semiconductor memory device 100 may transmit the outputDATA to the memory controller 400 through data buses corresponding totransmission lines using LVCMOS signaling and, simultaneously, maytransmit the FLAG signal indicating inversion of the output DATA to thememory controller 400.

When the operating frequency of the memory system 500 is a relativelyhigh operating frequency, the semiconductor memory device 100 may invertthe current internal output data and may output the inverted data as theoutput DATA when the number of “1” bits or “0” bits of the currentinternal output data is greater than half of the data width of thecurrent internal output data. In addition, the semiconductor memorydevice 100 may transmit the output DATA to the memory controller 400through the data buses using POD signaling and, simultaneously, maytransmit the FLAG signal indicating inversion of the output DATA to thememory controller 400.

Data write operations of the semiconductor memory device 100 will beexplained.

When the operating frequency of the memory system 500 is a relativelylow operating frequency, the memory controller 400 may invert currentinternal input data continuously read from the data register 402illustrated in FIG. 9 and may output the inverted data as input data(DATA) when the number of inverted bits of the current internal inputdata compared with the corresponding bits of output data right beforethe current internal output data is greater than half of the data widthof the current internal input data. In addition, the memory controller400 may transmit the input DATA to the semiconductor memory device 100through the data buses using LVCMOS signaling and, simultaneously, maytransmit the FLAG signal indicating inversion of the input DATA to thesemiconductor memory device 100.

When the operating frequency of the memory system 500 is a relativelyhigh operating frequency, the memory controller 400 may invert thecurrent internal input data and may output the inverted data as theinput DATA when the number of “1” bits or “0” bits of the currentinternal input data is greater than half of the data width of thecurrent internal input data. In addition, the memory controller 400 maytransmit the input DATA to the semiconductor memory device 100 throughthe data buses using POD signaling and, simultaneously, may transmit theFLAG signal indicating inversion of the input DATA to the semiconductormemory device 100.

Memory systems according to embodiments of the present invention mayselectively use LVCMOS signaling suitable for low-frequency operationand POD signaling suitable for high-frequency operation. Furthermore,memory systems according to embodiments of the present invention mayreduce AC power during LVCMOS signaling using a data inversion methodsuitable for LVCMOS signaling and may reduce DC power during PODsignaling using a data inversion method suitable for POD signaling.

In the drawings and specification, there have been disclosed embodimentsof the invention and, although specific terms are employed, they areused in a generic and descriptive sense only and not for purposes oflimitation, the scope of the invention being set forth in the followingclaims.

1. A method of communicating a plurality of groups of output data bitsrepresenting a respective plurality of groups of input data bits over adata bus wherein each group of output data bits and each group of inputdata bits have an equal data width, the method comprising: receivingeach of the plurality of groups of input data bits at a data register;for each group of input data bits received at the data register, if anumber of data bits of the group of input data bits that changes withrespect to respective data bits of a preceding group of output data bitsis greater than half of the data width, inverting the group of inputdata bits, transmitting the inverted group of input data bits as arespective group of output data bits in parallel over the data bus, andtransmitting an inversion flag associated with the respective group ofoutput data bits; and for each group of input data bits received at thedata register, if a number of data bits of the group of input data bitsthat remains unchanged with respect to respective data bits of apreceding group of output data bits is greater than half of the datawidth, transmitting the group of input data bits without inversion as arespective group of output data bits in parallel over the data bus, andtransmitting a non-inversion flag associated with the respective groupof output data bits.
 2. A method according to claim 1 wherein the databus includes a plurality of data transmission lines, whereintransmitting the respective groups of output data bits comprisestransmitting data bits of each respective group of output data bits overrespective ones of the data transmission lines.
 3. A method according toclaim 1 wherein receiving each of the plurality of groups of input databits comprises sequentially receiving each of the plurality of groups ofinput data bits at the data register.
 4. A method according to claim 1wherein the inversion and non-inversion flags are transmitted over thedata bus in parallel with the associated groups of output data bits. 5.A method according to claim 1 wherein receiving each of the plurality ofgroups of input data bits comprises receiving each of the plurality ofgroups of input data bits from a memory cell array of an integratedcircuit memory device during a read operation, wherein transmitting therespective groups of output data bits comprises transmitting therespective groups of output data bits from the integrated circuit memorydevice over the data bus to a memory controller.
 6. A method accordingto claim 5 further comprising: receiving the groups of output data bitsand the inversion and non-inversion flags at the memory controller.
 7. Amethod according to claim 1 wherein the data register comprises a dataregister of a memory controller, and wherein transmitting the respectivegroups of output data bits comprises transmitting the respective groupsof output data bits from the memory controller over the data bus to anintegrated circuit memory device during a write operation to write therespective groups of input data bits to a memory cell array of theintegrated circuit memory device.
 8. A method according to claim 7further comprising: receiving the groups of output data bits and theinversion and non-inversion flags at the integrated circuit memorydevice.
 9. A method according to claim 1 wherein receiving each of theplurality of groups of input data bits comprises receiving a firstplurality of groups of input data bits to be transmitted at a first datarate, and wherein transmitting each group of output data bitscorresponding to respective groups of input data bits of the firstplurality comprises transmitting each group of output data bits at thefirst data rate, the method further comprising: receiving each of asecond plurality of groups of input data bits at the data register to betransmitted at a second data rate different than the first data rate;for each group of input data bits of the second plurality received atthe data register, if a number of data bits of the group of input databits having a first logic level is greater than half of the data width,inverting the group of input data bits, transmitting the inverted groupof input data bits as a respective group of output data bits in parallelover the data bus at the second data rate, and transmitting an inversionflag associated with the respective group of output data bits; and foreach group of input data bits of the second plurality received at thedata register, if a number of data bits of the group of input data bitshaving a second logic level different than the first logic level isgreater than half of the data width, transmitting the group of inputdata bits without inversion as a respective group of output data bits inparallel over the data bus at the second data rate, and transmitting anon-inversion flag associated with the respective group of output databits.
 10. A method according to claim 9 wherein the first data rate isless than the second data rate.
 11. An electronic data systemcomprising: a data register configured to receive each of a plurality ofgroups of input data bits; an inversion controller coupled to the dataregister, wherein for each group of input data bits received at the dataregister, if a number of data bits of the group of input data bits thatchanges with respect to respective data bits of a preceding group ofoutput data bits is greater than half of the data width, the inversioncontroller is configured to invert the group of input data bits togenerate a respective group of output data bits, and wherein for eachgroup of input data bits received at the data register, if a number ofdata bits of the group of input data bits that remains unchanged withrespect to respective data bits of a preceding group of output data bitsis greater than half of the data width, the inversion controller isconfigured to generate a respective group of output data bits withoutinversion; an output driver coupled to the inversion controller whereinthe output driver is configured to transmit each respective group ofoutput data bits in parallel over a data bus; and a flag outputgenerator coupled to the inversion controller, wherein the flag outputgenerator is configured to transmit an inversion flag with each group ofoutput data bits generated by inverting the respective group of inputdata bits, and wherein the flag output generator is configured totransmit a non-inversion flag with each group of output data bitsgenerated without inverting the respective group of input data bits. 12.An electronic data system according to claim 11 wherein the data busincludes a plurality of data transmission lines, wherein transmittingthe respective groups of output data bits comprises transmitting databits of each respective group of output data bits over respective onesof the data transmission lines.
 13. An electronic data system accordingto claim 11 wherein the data register is configured to sequentiallyreceive each of the plurality of groups of input data bits at the dataregister.
 14. An electronic data system according to claim 11 whereinthe flag output generator is configured to transmit the inversion andnon-inversion flags over the data bus in parallel with the associatedgroups of output data bits.
 15. An electronic data system according toclaim 11 wherein the data register is further configured to receive eachof the plurality of groups of input data bits from a memory cell arrayof the electronic data system during a read operation, and to transmitthe respective groups of output data bits over the data bus to a memorycontroller.
 16. An electronic data system according to claim 11 whereinthe data register comprises a data register of a memory controller,wherein the data register is further configured to transmit therespective groups of output data bits over the data bus to an integratedcircuit memory device during a write operation to write the respectivegroups of input data bits to a memory cell array of the integratedcircuit memory device.